Single-Cycle Processor Design in Verilog
A single-cycle processor designed in Verilog for a computer organization and architecture course.
Hardware Design
Project Snapshot
| Signal | Details |
|---|---|
| Timeline | Feb 2015 to May 2015 |
| Organization | COMSATS University |
| Focus | Single cycle Processor design in Verilog |
| Stack | Verilog |
Architecture
Course: Computer Organization and Architecture.
- Designed both the data path and control path.
- Connected instruction memory, datapath components, and control logic into one execution flow.
- Built the processor to execute instructions stored in instruction memory, with support for up to
2^32instructions.